module ctrl(instruction,RegDst,RegWr,ExtOp,nPC_sel,ALUctr,MemtoReg,MemWr,ALUSrc,j_sel,rst);

  	input [31:0]instruction;
	input rst;
  	output reg [1:0]ExtOp,ALUctr,nPC_sel;
  	output reg RegDst,RegWr,MemtoReg,MemWr,ALUSrc,j_sel;
 

	always@(negedge rst)begin
    		nPC_sel=0;  //PC+4 or branch
    		RegDst=0;   //1=rd or 0=rt
    		RegWr=0;    //1=write at RegFile
    		ExtOp=0;    //00 nonsignal 01 signal 10 imm+0
    		ALUctr=0;
    		MemtoReg=0;
    		MemWr=0;
    		ALUSrc=0;
    		j_sel=0;
	end
	

	always@(*)begin
  		//R-type
		//6op 5rs 5rt 5rd 5shamt 6funct
  		if(instruction[31:26]==6'b000000)begin //op=000000
      			//ADD
      			if(instruction[5:0]==6'b100000)begin  //funct=32
          			nPC_sel=2'b00;
          			RegDst=1'b1;
          			RegWr=1'b1;
          			ExtOp=2'b00;
          			ALUSrc=1'b0;
          			ALUctr=2'b00;  //00->add
          			MemWr=1'b0;
          			MemtoReg=1'b0;
          			j_sel=1'b0;
      			end
      			//SUB
      			else if(instruction[5:0]==6'b100010)begin //funct=34
          			nPC_sel=2'b00;
          			RegDst=1'b1;
          			RegWr=1'b1;
          			ExtOp=2'b00;
          			ALUSrc=1'b0;
          			ALUctr=2'b01;  //01->sub
          			MemWr=1'b0;
          			MemtoReg=1'b0;
          			j_sel=1'b0;
        		end
			//ORU
      			else if(instruction[5:0]==6'b100101)begin //funct=37
          			nPC_sel=2'b00;
          			RegDst=1'b1;
          			RegWr=1'b1;
          			ExtOp=2'b00;
          			ALUSrc=1'b0;
          			ALUctr=2'b10;  //10->or
          			MemWr=1'b0;
          			MemtoReg=1'b0;
          			j_sel=1'b0;
        		end
			//ANDU
      			else if(instruction[5:0]==6'b100100)begin //funct=36
          			nPC_sel=2'b00;
          			RegDst=1'b1;
          			RegWr=1'b1;
          			ExtOp=2'b00;
          			ALUSrc=1'b0;
          			ALUctr=2'b11;  //11->and
          			MemWr=1'b0;
          			MemtoReg=1'b0;
          			j_sel=1'b0;
        		end
      		end
		
		//I-type 
		//6op 5rs 5rt 16address
      		//LW
    		else if(instruction[31:26]==6'b100011)begin //op=35
        		nPC_sel=2'b00;
          		RegDst=1'b0;
          		RegWr=1'b1;
          		ExtOp=2'b01;
          		ALUSrc=1'b1;
          		ALUctr=2'b00;
          		MemWr=1'b0;
          		MemtoReg=1'b1;
          		j_sel=1'b0;
        	end
        	//SW
      		else if(instruction[31:26]==6'b101011)begin //op=43
          		nPC_sel=2'b00;
          		RegDst=1'b0;
          		RegWr=1'b0;
          		ExtOp=2'b01;
          		ALUSrc=1'b1;
          		ALUctr=2'b00;
          		MemWr=1'b1;
          		MemtoReg=1'b0;
          		j_sel=1'b0;
        	end
        	//BEQ
      		else if(instruction[31:26]==6'b000100)begin //op=4
          		nPC_sel=2'b10; //ifu.v
          		RegDst=1'b0;
          		RegWr=1'b0;
          		ExtOp=2'b01;
          		ALUSrc=1'b0;
          		ALUctr=2'b01;  //sub
          		MemWr=1'b0;
          		MemtoReg=1'b0;
          		j_sel=1'b0;
        	end
        	//BNE
      		else if(instruction[31:26]==6'b000101)begin //op=5
          		nPC_sel=2'b11;  //ifu.v
          		RegDst=1'b0;
          		RegWr=1'b0;
          		ExtOp=2'b01;
          		ALUSrc=1'b0;
          		ALUctr=2'b01;  //sub
          		MemWr=1'b0;
          		MemtoReg=1'b0;
          		j_sel=1'b0;
        	end
    		//J
     		else if(instruction[31:26]==6'b000010)begin  //op=2  ifu.v
          		nPC_sel=2'b01;
          		RegDst=1'b0;
          		RegWr=1'b0;
          		ExtOp=2'b01;
          		ALUSrc=1'b0;
          		ALUctr=2'b01;
          		MemWr=1'b0;
          		MemtoReg=1'b1;
          		j_sel=1'b1;
    		end
      		//ORI
    		else if(instruction[31:26]==6'b001101)begin //op=13
        		nPC_sel=2'b00;
          		RegDst=1'b0;
          		RegWr=1'b1;
          		ExtOp=2'b00;
          		ALUSrc=1'b1;
          		ALUctr=2'b10;
          		MemWr=1'b0;
          		MemtoReg=1'b0;
          		j_sel=1'b0;
        	end
        	//LUI :16im+16*0
      		else if(instruction[31:26]==6'b001111)begin  
          		nPC_sel=2'b00;
          		RegDst=1'b0;
          		RegWr=1'b1;
          		ExtOp=2'b10;
          		ALUSrc=1'b1;
          		ALUctr=2'b10;
          		MemWr=1'b0;
          		MemtoReg=1'b0;
          		j_sel=1'b0;
      		end

  	end

endmodule
